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H8S/2240 数据表(PDF) 463 Page - Renesas Technology Corp

部件名 H8S/2240
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2240 数据表(HTML) 463 Page - Renesas Technology Corp

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Section 12 Serial Communication Interface (SCI)
Rev.3.00 Mar. 26, 2007 Page 421 of 772
REJ09B0355-0300
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid in clocked synchronous mode, when multiprocessor format is not
used, and when the operation is not transmission.
Bit 0
MPBT
Description
0
Data with a 0 multiprocessor bit is transmitted
(Initial value)
1
Data with a 1 multiprocessor bit is transmitted
12.2.8
Bit Rate Register (BRR)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
R/W
:
:
:
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset, and in standby mode or module stop mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 12.3 shows sample BRR settings in asynchronous mode, and table 12.4 shows sample BRR
settings in clocked synchronous mode.



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