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H8S/2240 数据表(PDF) 703 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 703 Page - Renesas Technology Corp |
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703 / 818 page ![]() Appendix B Register Field Rev.3.00 Mar. 26, 2007 Page 661 of 772 REJ09B0355-0300 SYSCR—System Control Register H'FF39 MCU 7 — 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 0 RAME 1 R/W 2 — 0 — 1 — 0 — Bit Initial value Read/Write : : : Interrupt Control Mode Selection 0 1 0 1 0 1 Interrupt control mode 0 Interrupt control mode 1 Setting prohibited Setting prohibited NMI Input Edge Select 0 1 Falling edge Rising edge RAM Enable* 0 1 On-chip RAM disabled On-chip RAM enabled Note: * When the DTC is used, the RAME bit should not be cleared to 0. |
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