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数据搜索系统，热门电子元器件搜索 |
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H8S/2240 数据表(PDF) 716 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 716 Page - Renesas Technology Corp |
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716 / 818 page  Appendix B Register Field Rev.3.00 Mar. 26, 2007 Page 674 of 772 REJ09B0355-0300 SMR0—Serial Mode Register 0 H'FF78 SCI0 7 C/ A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/ E 0 R/W 3 STOP 0 R/W 0 CKS0 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 1 Asynchronous mode Synchronous mode Asynchronous Mode/Synchronous Mode Select 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Parity Enable 0 1 Even parity Odd parity Parity Mode 0 1 0 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock Clock Select 0 1 Multiprocessor function disabled Multiprocessor format selected Multiprocessor Mode 0 1 1 stop bit 2 stop bits Stop Bit Length 0 1 8-bit data 7-bit data* Character Length Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Bit Initial value Read/Write : : : |
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