H8SSLASH2240 datasheet(238/818 Pages) RENESAS

部件名	H8S/2240

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

PDF	818 Pages

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制造商	RENESAS [Renesas Technology Corp]

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Section 7 Data Transfer Controller

Rev.3.00 Mar. 26, 2007 Page 196 of 772

REJ09B0355-0300

7.3.6

Repeat Mode

In repeat mode, one operation transfers one byte or one word of data.

From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the

initial states of the transfer counter and the address register specified as the repeat area are

restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00,

and therefore CPU interrupts cannot be requested when DISEL = 0.

Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in

repeat mode.

Table 7.6

Name

Abbreviation

Function

DTC source address register

SAR

Designates source address

DTC destination address register

DAR

Designates destination address

DTC transfer count register AH

CRAH

Holds number of transfers

DTC transfer count register AL

CRAL

Designates transfer count

DTC transfer count register B

CRB

Not used

Transfer

SAR or

DAR

DAR or

SAR

Figure 7.7 Memory Mapping in Repeat Mode

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