H8SXSLASH1663 datasheet(413/1158 Pages) RENESAS

413 / 1158 page

Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 361 of 1102

REJ09B0294-0100

(2) XY Conversion Using Offset

Figure 7.19 shows the XY conversion using the offset addition in repeat transfer mode.

Data 1

Data 2

Data 3

Data 4

Data 5

Data 11

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Data 16

Data 15

Data 14

Data 13

Data 10

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Data 1

Data 5

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Data 13

Data 2

Data 11

Data 15

Data 12

Data 8

Data 4

Data 7

Data 3

Data 14

Data 10

Data 6

1st transfer

2nd transfer

3rd transfer

4th transfer

1st transfer

2nd transfer

3rd transfer

4th transfer

Data 1

Data 2

Data 3

Data 4

Data 15

Data 5

Data 11

Data 12

Data 16

Data 14

Data 13

Data 10

Data 9

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Data 6

Data 1

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Data 3

Data 4

Data 15

Data 5

Data 11

Data 12

Data 16

Data 14

Data 13

Data 10

Data 9

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Data 6

Data 1

Data 2

Data 3

Data 4

Data 15

Data 5

Data 11

Data 12

Data 16

Data 14

Data 13

Data 10

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Data 1

Data 5

Data 9

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Data 12

Data 2

Data 11

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Data 16

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Data 7

Data 3

Data 14

Data 10

Data 6

Transfer

Interrupt

request

generated

Interrupt

request

generated

Address

initialized

Interrupt

request

generated

Address

initialized

Transfer source

addresses

changed

by CPU

Transfer source

addresses

changed

by CPU

Offset

Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode

In figure 7.19, the source address side is specified to the repeat area by DACR and the offset

addition is selected. The offset value is set to 4

× data access size (when the data access size is

longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4

× data access

size (when the data access size is longword, the repeat size is set to 4

× 4 = 16 bytes, as an

example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address.

A repeat size end interrupt is requested when the repeat size of transfers is completed.

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