H8SXSLASH1663 datasheet(456/1158 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 404 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

RRS

R/W

DTC Transfer Information Read Skip Enable

Controls the vector address read and transfer

information read. A DTC vector number is always

compared with the vector number for the previous

activation. If the vector numbers match and this bit is

set to 1, the DTC data transfer is started without

reading a vector address and transfer information. If the

previous DTC activation is a chain transfer, the vector

address read and transfer information read are always

performed.

0: Transfer read skip is not performed.

1: Transfer read skip is performed when the vector

numbers match.

RCHNE

R/W

Chain Transfer Enable After DTC Repeat Transfer

Enables/disables the chain transfer while transfer

counter (CRAL) is 0 in repeat transfer mode.

In repeat transfer mode, the CRAH value is written to

CRAL when CRAL is 0. Accordingly, chain transfer may

not occur when CRAL is 0. If this bit is set to 1, the

chain transfer is enabled when CRAH is written to

CRAL.

0: Disables the chain transfer after repeat transfer

1: Enables the chain transfer after repeat transfer

2, 1



All 0

Reserved

These are read-only bits and cannot be modified.

ERR

R/(W)* Transfer Stop Flag

Indicates that an address error or an NMI interrupt

occurs. If an address error or an NMI interrupt occurs,

the DTC stops.

0: No interrupt occurs

1: An interrupt occurs

[Clearing condition]

• When writing 0 after reading 1

Note:

Only 0 can be written to clear this flag.

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