H8SXSLASH1663 datasheet(493/1158 Pages) RENESAS

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Section 9 I/O Ports

Rev.1.00 Jun. 07, 2006 Page 441 of 1102

REJ09B0294-0100

9.1.6

Open-Drain Control Register (PnODR) (n = 2 and F)

ODR is an 8-bit readable/writable register that selects the open-drain output function.

If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS open-

drain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as

a CMOS output.

The initial value of ODR is H'00.

Bit

Bit Name

Initial Value

R/W

Pn7ODR

R/W

Pn6ODR

R/W

Pn5ODR

R/W

Pn4ODR

R/W

Pn3ODR

R/W

Pn2ODR

R/W

Pn1ODR

R/W

Pn0ODR

R/W

9.2

Output Buffer Control

This section describes the output priority of each pin.

The name of each peripheral module pin is followed by "_OE". This (for example: TIOCA4_OE)

indicates whether the output of the corresponding function is valid (1) or if another setting is

specified (0). Table 9.5 lists each port output signal's valid setting. For details on the

corresponding output signals, see the register description of each peripheral module. If the name

of each peripheral module pin is followed by A or B, the pin function can be modified by the port

function control register (PFCR). For details, see section 9.3, Port Function Controller.

For a pin whose initial value changes according to the activation mode, "Initial value E" indicates

the initial value when the LSI is started up in external extended mode and "Initial value S"

indicates the initial value when the LSI is started in single-chip mode.

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