H8SXSLASH1663 datasheet(634/1158 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 582 of 1102

REJ09B0294-0100

10.10.12 Conflict between TCNT Write and Overflow/Underflow

If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write

cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.

Figure 10.54 shows the operation timing when there is conflict between TCNT write and

overflow.

TCNT

H'FFFF

TCFV flag

Address

Write

TCNT address

TCNT write data

TGR write cycle

Figure 10.54 Conflict between TCNT Write and Overflow

10.10.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin

with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input

pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not

be performed from a multiplexed pin.

10.10.14 Interrupts and Module Stop Mode

If module stop state is entered when an interrupt has been requested, it will not be possible to clear

the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be

disabled before entering module stop state.

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