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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663 数据表(PDF) 937 Page - Renesas Technology Corp |
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H8SX/1663 数据表(HTML) 937 Page - Renesas Technology Corp |
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937 / 1158 page  Section 21 Flash Memory (0.18- µm F-ZTAT Version) Rev.1.00 Jun. 07, 2006 Page 885 of 1102 REJ09B0294-0100 Table 21.3 Registers/Parameters and Target Modes Register/Parameter Down- load Initiali- zation Program- ming Erasure Read RAM Emulation FCCS O FPCS O FECS O FKEY O O O Programming/ erasing interface registers FTDAR O DPFR O FPFR O O O FPEFEQ O FMPAR O FMPDR O Programming/ erasing interface parameters FEBS O RAM emulation RAMER O 21.6.1 Programming/Erasing Interface Registers The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. (1) Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM. 7 1 R 6 0 R 5 0 R 4 FLER 0 R 3 0 R 0 SCO 0 (R)/W 2 0 R 1 0 R Bit Bit Name Initial Value R/W |
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