H8SXSLASH1663 datasheet(956/1158 Pages) RENESAS

956 / 1158 page

Section 21 Flash Memory (0.18-

µm F-ZTAT Version)

Rev.1.00 Jun. 07, 2006 Page 904 of 1102

REJ09B0294-0100

(1) Serial Interface Setting by Host

The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data,

one stop bit, and no parity.

When a transition to SCI boot mode is made, the boot program embedded in this LSI is initiated.

When the boot program is initiated, this LSI measures the low period of asynchronous serial

communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and

adjusts the bit rate of the SCI_4 to match that of the host.

When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit

adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1

byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The

bit rate may not be adjusted within the allowable range depending on the combination of the bit

rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the

host and the system clock frequency of this LSI must be as shown in table 21.6.

Start

bit

Stop bit

Measure low period (9 bits) (data is H'00)

High period of

at least 1 bit

Figure 21.7 Automatic-Bit-Rate Adjustment Operation

Table 21.6

System Clock Frequency for Automatic-Bit-Rate Adjustment

Bit Rate of Host

System Clock Frequency of This LSI

9,600 bps

8 to 18 MHz

19,200 bps

8 to 18 MHz

H8SX/1663 数据表(PDF) 956 Page - Renesas Technology Corp