H8SXSLASH1663 datasheet(1044/1158 Pages) RENESAS

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Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 992 of 1102

REJ09B0294-0100

23.10

φ Clock Output Control

Output of the

φ clock (Bφ/SDφ) can be controlled by bits PSTOP1, and PSTOP0 in SCKCR, and

DDR for the corresponding port. Bits PSTOP1 control the B

φ clock output on the PA7 pin. Bit

PSTOP0 controls the SD

φ clock output on the PB7 pin. When bit PSTOP1 is set to 1, the Bφ clock

output stops at the end of the bus cycle and goes high. In the same way, bit PSTOP0 drives the

φ clock output on the PB7 pin high. When DDR for the PA7 pin is cleared to 0, the Bφ clock

output is disabled and the pin becomes an input port. When the SDRAM interface is disabled, the

PB7 pin can be used as I/O port. Tables 23.3 and 23.4 show the states of the

φ pin in each

processing state.

Table 23.3

φ Pin (PA7) State in Each Processing State

Software Standby

Mode

DDR

PSTOP1

Normal

Operating

State

Sleep

Mode

All-

Module-

Clock-

Stop Mode OPE = 0

OPE = 1

Hardware

Standby

Mode

Hi-Z

φ output

High

Hi-Z

High

Hi-Z

Table 23.4

φ Pin (PB7) State in Each Processing State (SDRAM Interface Enabled)

Software Standby

Mode

PSTOP0

Normal

Operating

State

Sleep

Mode

All-

Module-

Clock-

Stop Mode OPE = 0

OPE = 1

Hardware

Standby

Mode

φ output SDφ output SDφ output High

High

Hi-Z

High

Hi-Z

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