H8SXSLASH1663 datasheet(1059/1158 Pages) RENESAS

1059 / 1158 page

Section 24 List of Registers

Rev.1.00 Jun. 07, 2006 Page 1007 of 1102

REJ09B0294-0100

Abbreviation

Number

of Bits

Address

Module

Data

Width

Access

Cycles

(Read/Write)

Timer I/O control register H_3

TIORH_3

H'FFFF2

TPU_3

φ/2Pφ

Timer I/O control register L_3

TIORL_3

H'FFFF3

TPU_3

φ/2Pφ

Timer interrupt enable register_3

TIER_3

H'FFFF4

TPU_3

φ/2Pφ

Timer status register_3

TSR_3

H'FFFF5

TPU_3

φ/2Pφ

Timer counter_3

TCNT_3

H'FFFF6

TPU_3

φ/2Pφ

Timer general register A_3

TGRA_3

H'FFFF8

TPU_3

φ/2Pφ

Timer general register B_3

TGRB_3

H'FFFFA

TPU_3

φ/2Pφ

Timer general register C_3

TGRC_3

H'FFFFC

TPU_3

φ/2Pφ

Timer general register D_3

TGRD_3

H'FFFFE

TPU_3

φ/2Pφ

Note:

When the same output trigger is specified for pulse output groups 2 and 3 by the PCR

setting, the NDRH address is H'FFF7C. When different output triggers are specified, the

NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C,

respectively. Similarly, When the same output trigger is specified for pulse output

groups 0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different

output triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are

H'FFF7F and H'FFF7D, respectively.

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