H8SXSLASH1663 datasheet(1147/1158 Pages) RENESAS

1147 / 1158 page

Rev.1.00 Jun. 07, 2006 Page 1095 of 1102

REJ09B0294-0100

Index

Numerics

φ clock output control ............................. 992

0-output/1-output .................................... 540

16-bit access space.................................. 190

16-bit counter mode................................ 628

16-bit timer pulse unit (TPU).................. 497

32K timer (TM32K) ............................... 637

8-bit access space.................................... 189

8-bit timers (TMR) ................................. 605

A/D conversion accuracy........................ 861

A/D converter ......................................... 849

Absolute accuracy................................... 861

Acknowledge .......................................... 833

Address error ............................................ 84

Address map ............................................. 73

Address modes........................................ 343

Address/data multiplexed I/O

interface .......................................... 182, 218

All-module-clock-stop mode .................. 972

Area 0 ..................................................... 184

Area 1 ..................................................... 185

Area 2 ..................................................... 185

Area 3 ..................................................... 186

Area 4 ..................................................... 186

Area 5 ..................................................... 187

Area 6 ..................................................... 188

Area 7 ..................................................... 188

Area division........................................... 177

Asynchronous mode ............................... 698

AT-cut parallel-resonance type............... 963

Available output signal and settings

in each port ............................................. 476

Average transfer rate generator............... 654

Basic bus interface .......................... 181, 192

Big endian ............................................... 180

Bit rate..................................................... 681

Bit synchronous circuit ........................... 847

Block diagram............................................. 2

Block structure ........................................ 879

Block transfer mode........................ 349, 417

Boot mode....................................... 877, 903

Buffer operation ...................................... 545

Bulk-in transfer ....................................... 802

Bulk-out transfer ..................................... 801

Burst access mode................................... 355

Burst ROM interface....................... 181, 213

Bus access modes.................................... 354

Bus arbitration......................................... 311

Bus configuration.................................... 168

Bus controller (BSC)............................... 131

Bus cycle division ................................... 411

Bus release .............................................. 304

Bus width ................................................ 180

Byte control SRAM interface ......... 181, 205

Cascaded connection............................... 628

Cascaded operation ................................. 549

Chain transfer.......................................... 418

Chip select signals................................... 178

Clock pulse generator.............................. 957

Clock synchronization cycle (Tsy).......... 170

Clocked synchronous mode .................... 715

Communications protocol....................... 932

Compare match A ................................... 626

Compare match B ................................... 627

Compare match count mode ................... 629

Compare match signal............................. 626

H8SX/1663 数据表(PDF) 1147 Page - Renesas Technology Corp

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