H8SXSLASH1663R datasheet(335/1504 Pages) RENESAS

335 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 303 of 1468

REJ09B0412-0200

(3)

Refresh and All-Module Clock Stop Mode

This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of

all on-chip peripheral modules by setting the ACSE bit in MSTPCR to 1 (MSTPCRA, MSTPCRB

= H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), then

execute the SLEEP instruction to enter the sleep mode.

In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the

clock for the bus controller is stopped, a CBR refresh cycle cannot be performed. When external

DRAM is used and the contents of the DRAM in sleep mode should be held, clear the ACSE bit in

MSTPCE to 0.

For details, see section 28.2.2, Module Stop Control Registers A and B (MSTPCRA and

MSTPCRB).

9.10.13

DRAM Interface and Single Address Transfer by DMAC and EXDMAC

When fast-page mode (BE = 1) is set for the DRAM space, either fast-page access or full access

can be selected, by the setting of bits DDS and EDDS in DRAMCR, for the single address transfer

by the DMAC or EXDMAC where the DRAM space is specified as the transfer source or

destination. At the same time, the output timings of the

DACK, EDACK and BS signals are

changed. When BE

= 0, full access to the DRAM space is performed by single address transfer

regardless of the setting of bits DDS and EDDS. However, the output timing of the

DACK,

EDACK and BS signals can be changed by the setting of bits DDS and EDDS.

The assertion timing of the

DACK and EDACK signal can be changed by bits DKC and EDKC in

BCR1.

H8SX/1663R 数据表(PDF) 335 Page - Renesas Technology Corp