H8SXSLASH1663R datasheet(368/1504 Pages) RENESAS

368 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 336 of 1468

REJ09B0412-0200

Figure 9.82 shows the timing of setting SDRAM mode register.

RAS

CAS

CKE

High

Mode register setting

High

RD/

High

PALL

NOP

MRS

NOP

Precharge-sel

Address bus

SDRAM

Figure 9.82 Timing of Setting SDRAM Mode Register

9.11.15

SDRAM Interface and Single Address Transfer by DMAC and EXDMAC

When fast-page mode (BE = 1) is set for the SDRAM space, either fast-page access or full access

can be selected, by the setting of bits DDS and EDDS in DRAMCR, for the single address transfer

by the DMAC or EXDMAC where the SDRAM space is specified as the transfer source or

destination. At the same time, the output timing of the

DACK and EDACK and BS signals can be

changed. When BE

= 0, a full access to the SDRAM space is performed with a single address

transfer regardless of the setting of bits DDS and EDDS. However, the output timing of the

DACK, EDACK and BS signals can be changed by the setting of bits DDS and EDDS.

The assertion timing of the

DACK and EDACK signals can be changed by the bits DKC and

EDKC in BCR1.

The output timing of the

DACK and EDACK signals can be independently set by the bits TRWL

and CKSPE in SDCR and bit DKC and EDKC in BCR1 regardless of the setting of bits DDS and

EDDS.

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