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H8SX/1663R 数据表(PDF) 391 Page - Renesas Technology Corp |
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H8SX/1663R 数据表(HTML) 391 Page - Renesas Technology Corp |
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391 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 359 of 1468 REJ09B0412-0200 9.12.2 Pin States in Idle Cycle Table 9.31 shows the pin states in an idle cycle. Table 9.31 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance CSn (n = 7 to 0) High* 1 LUCAS, LLCAS High DQMLU, DQMLL High* 2 AS High RD High BS High RD/ WR High* 3 AH low LHWR, LLWR High LUB, LLB High CKE High OE High RAS High/Low* 4 CAS High WE High DACKn (n = 3 to 0) High EDACKn (n = 3 to 0) High Notes: 1. Low when accessing the SDRAM in full access cycle 2. Low when reading the SDRAM in full access cycle 3. Low when accessing or writing to the DRAM/SDRAM in full access cycle 4. The pin state varies depending on the DRAM space access/ area access other than the DRAM space, or RAS up mode/RAS down mode. For details, see figures 9.98 and 9.100. |
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