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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663R 数据表(PDF) 520 Page - Renesas Technology Corp |
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H8SX/1663R 数据表(HTML) 520 Page - Renesas Technology Corp |
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520 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 488 of 1468 REJ09B0412-0200 Figure 11.10 shows an example of EXDMA transfer timing in block transfer mode. The transfer conditions are as follows: Address mode: Single address mode Data access size: In bytes One block size: 3 bytes Figure 11.11 shows the block transfer mode operation in single address mode and figure 11.12 shows the block transfer mode operation in dual address mode. CPU CPU EXDMAC EXDMAC EXDMAC CPU Bus cycle ETEND EDREQ CPU cycle not generated One-block transfer cycle EDRAK Figure 11.10 Example of Block Transfer Mode Transfer Address T Address B EDACK Block BKSZH × data access size Figure 11.11 Block Transfer Mode Operation in Single Address Mode (with Block Area Specified) |
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