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H8SX/1663R 数据表(PDF) 569 Page - Renesas Technology Corp

部件名 H8SX/1663R
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663R 数据表(HTML) 569 Page - Renesas Technology Corp

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Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 537 of 1468
REJ09B0412-0200
11.6.3
Caution for Combining with Extended Repeat Area Function
As with the block transfer mode, the address register value must be set in cluster transfer mode, so
that the end of the cluster size coincides with the end of the extended repeat area range.
When an extended repeat area overflow occurs during a cluster-size transfer in the cluster transfer
mode, the extended repeat area overflow interrupt request is held pending until the end of a
cluster-size transfer, and transfer overrun will occur.
11.6.4
Bus Cycles in Cluster Transfer Dual Address Mode
(1)
Cluster transfer mode
In cluster transfer mode, a cluster-size transfer is processed in response to one transfer request.
In an example shown in figure 11.61, the
ETEND pin output is enabled, and word-size transfer is
performed with 4-byte cluster size in cluster transfer mode from the external 16-bit, 2-state access
space to the external 16-bit, 2-state access space.
EXDMA read
EXDMA read
EXDMA write
EXDMA write
Bus
release
B
φ
Address bus
LHWR,
LLWR
ETEND
RD
Figure 11.61 Example of Cluster Transfer Mode Transfer



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