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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663R 数据表(PDF) 817 Page - Renesas Technology Corp |
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H8SX/1663R 数据表(HTML) 817 Page - Renesas Technology Corp |
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817 / 1504 page  Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Sep. 24, 2008 Page 785 of 1468 REJ09B0412-0200 • PODRL Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set. • PODRH_1 Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 POD31 POD30 POD29 POD28 POD27 POD26 POD25 POD24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 31 to 24 For bits which have been set to pulse output by NDERH_1, the output trigger transfers NDRH_1 values to this register during PPG operation. While NDERH_1 is set to 1, the CPU cannot write to this register. While NDERH_1 is cleared, the initial output value of the pulse can be set. |
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