H8SXSLASH1663R datasheet(912/1504 Pages) RENESAS

912 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 880 of 1468

REJ09B0412-0200

19.3.6

Serial Control Register (SCR)

SCR is a register that enables/disables the following SCI transfer operations and interrupt requests,

and selects the transfer clock source. For details on interrupt requests, see section 19.9, Interrupt

Sources. Some bits in SCR have different functions in normal mode and smart card interface

mode.

• When SMIF in SCMR = 0

TIE

R/W

RIE

R/W

MPIE

R/W

TEIE

R/W

CKE1

R/W

CKE0

R/W

Bit

Bit Name

Initial Value

R/W

• When SMIF in SCMR = 1

TIE

R/W

RIE

R/W

MPIE

R/W

TEIE

R/W

CKE1

R/W

CKE0

R/W

Bit

Bit Name

Initial Value

R/W

Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When this bit is set to 1, a TXI interrupt request is

enabled.

A TXI interrupt request can be cancelled by reading 1

from the TDRE flag and then clearing the flag to 0, or by

clearing the TIE bit to 0.

RIE

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests

are enabled.

RXI and ERI interrupt requests can be cancelled by

reading 1 from the RDRF, FER, PER, or ORER flag and

then clearing the flag to 0, or by clearing the RIE bit to 0.

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