H8SXSLASH1663R datasheet(924/1504 Pages) RENESAS

部件名	H8SX/1663R

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

924 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 892 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

PER

R/(W)* Parity Error

Indicates that a parity error has occurred during reception

in asynchronous mode and the reception ends

abnormally.

[Setting condition]

• When a parity error is detected during reception

Receive data when the parity error occurs is

transferred to RDR, however, the RDRF flag is not

set. Note that when the PER flag is being set to 1, the

subsequent serial reception cannot be performed. In

clocked synchronous mode, serial transmission also

cannot continue.

[Clearing condition]

• When 0 is written to PER after reading PER = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

Even when the RE bit in SCR is cleared, the PER flag

is not affected and retains its previous value.

H8SX/1663R 数据表(PDF) 924 Page - Renesas Technology Corp