H8SXSLASH1663R datasheet(946/1504 Pages) RENESAS

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Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 914 of 1468

REJ09B0412-0200

19.4.2

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times* the bit rate.

In reception, the SCI samples the falling edge of the start bit using the base clock, and performs

internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse* of the

base clock, data is latched at the middle of each bit, as shown in figure 19.6. Thus the reception

margin in asynchronous mode is determined by formula (1) below.

M = | (0.5 –

) – (L – 0.5) F –

+ F ) | × 100

[%]

... Formula (1)

| D – 0.5 |

M: Reception margin

N: Ratio of bit rate to clock (When ABCS = 0, N = 16. When ABCS = 1, N = 8.)

D: Duty cycle of clock (D = 0.5 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute value of clock frequency deviation

[Legend]

Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the

formula below.

M = ( 0.5 –

) × 100

[%] = 46.875%

2 × 16

However, this is only the computed value, and a margin of 20% to 30% should be allowed in

system design.

Internal basic

clock

16 clocks

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Start bit

Data sampling

timing

15 0

Figure 19.6 Receive Data Sampling Timing in Asynchronous Mode

Note: * This is an example when the ABCS bit in SEMR_2, 5, and 6 is 0. When the ABCS bit

is 1, a frequency of 8 times the bit rate is used as a base clock and receive data is

sampled at the rising edge of the 4th pulse of the base clock.

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