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H8SX/1663R 数据表(PDF) 1081 Page - Renesas Technology Corp

部件名 H8SX/1663R
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663R 数据表(HTML) 1081 Page - Renesas Technology Corp

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Section 21 I
2C Bus Interface 2 (IIC2)
Rev. 2.00 Sep. 24, 2008 Page 1049 of 1468
REJ09B0412-0200
21.3.7
I
2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects a
space in the I
2C bus shift register, it transfers the transmit data which has been written to ICDRT
to ICDRS and starts transmitting data. If the next data is written to ICDRT during transmitting
data to ICDRS, continuous transmission is possible.
Bit
Bit Name
Initial Value
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
21.3.8
I
2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit read-only register that stores the receive data. When one byte of data has been
received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be
received. ICDRR is a receive-only register; therefore, this register cannot be written to by the
CPU.
Bit
Bit Name
Initial Value
R/W
7
1
R
6
1
R
5
1
R
4
1
R
3
1
R
2
1
R
1
1
R
0
1
R
21.3.9
I
2C Bus Shift Register (ICDRS)
ICDRS is an 8-bit register that is used to transmit/receive data. In transmission, data is transferred
from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred
from ICDRS to ICDRR after one by of data is received. This register cannot be read from or
written to by the CPU.
Bit
Bit Name
Initial Value
R/W
7
0
−
6
0
−
5
0
−
4
0
−
3
0
−
2
0
−
1
0
−
0
0
−



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