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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663R 数据表(PDF) 1286 Page - Renesas Technology Corp |
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H8SX/1663R 数据表(HTML) 1286 Page - Renesas Technology Corp |
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1286 / 1504 page  Section 28 Power-Down Modes Rev. 2.00 Sep. 24, 2008 Page 1254 of 1468 REJ09B0412-0200 Bit Bit Name Initial Value R/W Module 4 DLVDIF* 2 0 R/(W)* 1 LVD Interrupt Flag [Setting condition] Voltage monitoring interrupt is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1. 3 DIRQ3F 0 R/(W)* 1 IRQ3 Interrupt Flag [Setting condition] IRQ3-A input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1. 2 DIRQ2F 0 R/(W)* 1 IRQ2 Interrupt Flag [Setting condition] IRQ2-A input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1. 1 DIRQ1F 0 R/(W)* 1 IRQ1 Interrupt Flag [Setting condition] IRQ1-A input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1. 0 DIRQ0F 0 R/(W)* 1 IRQ0 Interrupt Flag [Setting condition] IRQ0-A input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1. Note: 1. Only 0 can be written to clear the flag. 2. Supported only by the H8SX/1668M Group. |
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