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H8SX/1663R 数据表(PDF) 199 Page - Renesas Technology Corp

部件名 H8SX/1663R
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663R 数据表(HTML) 199 Page - Renesas Technology Corp

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Section 7 Interrupt Controller
Rev. 2.00 Sep. 24, 2008 Page 167 of 1468
REJ09B0412-0200
Table 7.8 shows a setting example of the priority control function over the DTC, DMAC and
EXDMAC, and the transfer request control state. A priority level can be independently set to each
DMAC and EXDMAC channel, but the table only shows one channel for example. Transfers
through the DMAC and EXDMAC channels can be separately controlled by assigning different
priority levels for channels.
Table 7.8
Example of Priority Control Function Setting and Control State
Transfer Request Control State
Interrupt
Control
Mode
CPUPCE in
CPUPCR
CPUP2 to
CPUP0
DTCP2 to
DTCP0
DMAP2 to
DMAP0
EDMAP2 to
EDMAP0
DTC
DMAC
EXDMAC
0
0
Any
Any
Any
Any
Enabled Enabled
Enabled
1
B'000
B'000
B'000
B'000
Enabled Enabled
Enabled
B'100
B'000
B'000
B'000
Masked
Masked
Masked
B'100
B'000
B'011
B'100
Masked
Masked
Enabled
B'100
B'111
B'101
B'000
Enabled Enabled
Masked
B'000
B'111
B'101
B'000
Enabled Enabled
Enabled
2
0
Any
Any
Any
Any
Enabled Enabled
Enabled
1
B'000
B'000
B'000
B'000
Enabled Enabled
Enabled
B'000
B'011
B'101
B'110
Enabled Enabled
Enabled
B'011
B'011
B'101
B'110
Enabled Enabled
Enabled
B'100
B'011
B'101
B'110
Masked
Enabled
Enabled
B'101
B'011
B'101
B'110
Masked
Enabled
Enabled
B'110
B'011
B'101
B'110
Masked
Masked
Enabled
B'111
B'011
B'101
B'110
Masked
Masked
Masked
B'101
B'011
B'101
B'011
Masked
Enabled
Masked
B'101
B'110
B'101
B'011
Enabled Enabled
Masked



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