H8SXSLASH1663R datasheet(212/1504 Pages) RENESAS

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Section 8 User Break Controller (UBC)

Rev. 2.00 Sep. 24, 2008 Page 180 of 1468

REJ09B0412-0200

8.5

Usage Notes

1. PC break usage note

 Contention between a SLEEP instruction (to place the chip in the sleep state or on software

standby) and PC break

If a break before a PC break instruction is set for the instruction after a SLEEP instruction

and the SLEEP instruction is executed with the SSBY bit cleared to 0, break interrupt

exception handling is executed without sleep mode being entered. In this case, the

instruction after the SLEEP instruction is executed after the RTE instruction.

When the SSBY bit is set to 1, break interrupt exception handling is executed after the

oscillation settling time has elapsed subsequent to the transition to software standby mode.

When an interrupt is the canceling source, interrupt exception handling is executed after the

RTE instruction, and the instruction following the SLEEP instruction is then executed.

SLEEP

Break interrupt

exception handling

Interrupt

exception handling

Software standby

(PC break source)

(Cancelling source)

Cancelling source

CLK

Figure 8.2 Contention between SLEEP Instruction (Software Standby) and PC Break

2. Prohibition on Setting of PC Break

 Setting of a UBC break interrupt for program within the UBC break interrupt handling

routine is prohibited.

3. The procedure for clearing a UBC flag bit (condition match flag) is shown below. A flag bit is

cleared by writing 0 to it after reading it as 1. As the register that contains the flag bits is

accessible in byte units, bit manipulation instructions can be used.

H8SX/1663R 数据表(PDF) 212 Page - Renesas Technology Corp