H8SXSLASH1663R datasheet(243/1504 Pages) RENESAS

部件名	H8SX/1663R

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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243 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 211 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

EDDS

R/W

EXDMAC Single Address Transfer Option

Selects whether an EXDMAC single address transfer

through the DRAM/SDRAM interface is enabled only in

full access mode or is also enabled in fast-page access

mode.

When clearing the BE bit to 0 to disable a burst access

to the DRAM/SDRAM interface, an EXDMAC single

address transfer is performed in full access mode

regardless of this bit.

This bit does not affect an external access by other bus

masters or an EXDMAC dual address transfer. Setting

this bit to 1 changes the EDACK output timing.

0: EXDMAC single address transfer through the

DRAM/SDRAM is enabled only in full access mode

1: EXDMAC single address transfer through the

DRAM/SDRAM is also enabled in fast-page access

mode



R/W

Reserved

The initial value should not be changed.

H8SX/1663R 数据表(PDF) 243 Page - Renesas Technology Corp