M30620FCAFP datasheet(486/615 Pages) RENESAS

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Multiple Interrupts

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-169

Table 2.14.2. Interrupt levels enabled according

to the contents of the IPL

Table 2.14.1. Settings of interrupt priority levels

When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt

in the following timing:

• When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction

that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.

• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes

effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the

instruction used.

• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes

effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in

the instruction used.

(5) Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (check-

ing whether interrupt requests are made), the interrupt assigned a higher priority is accepted.

Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority

level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher

hardware priority is accepted.

Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest

priority), watchdog timer interrupt, etc. are regulated by hardware.

Figure 2.14.4 shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control

branches invariably to the interrupt routine.

Interrupt priority

level select bit

Interrupt priority

level

Priority

order

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

b2 b1 b0

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL2 IPL1 IPL0

IPL

Figure 2.14.4. Hardware interrupts priorities

_______

________

Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL

are independent, and they are not affected by one another.

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