M38041F1HKP datasheet(139/387 Pages) RENESAS

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2-15

APPLICATION

2.2 Interrupt

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

(2)

Timing after acceptance of interrupt request

The interrupt processing routine begins with the machine cycle following the completion of the

instruction that is currently being executed.

Figure 2.2.10 shows the time up to execution of interrupt processing routine and Figure 2.2.11 shows

the timing chart after acceptance of interrupt request.

Fig. 2.2.11 Timing chart after acceptance of interrupt request

Fig. 2.2.10 Time up to execution of interrupt processing routine

Interrupt request generated

Main routine

Interrupt processing routine

7 to 23 cycles

(When f(XIN) = 8 MHz, 1.75

µs to 5.75 µs)

2 cycles

5 cycles

Start of interrupt processing

0 to 16 cycles

Waiting time for

post-processing

of pipeline

Stack push and

Vector fetch

✽

✽ When executing DIV instruction

PCH

PCL

PSAL

S, SPS

S-2, SPS

S-1, SPS

AL, AH

: CPU operation code fetch cycle

(This is an internal signal that cannot be observed from the external unit.)

: Vector address of each interrupt

: Jump destination address of each interrupt

: “0016” or “0116”

SYNC

BL, BH

AL, AH

SPS

Data bus

Not used

Address bus

SYNC

Waiting time for pipeline

post-processing

Push onto stack

Vector fetch

Interrupt operation starts

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