M38041FEHKP datasheet(141/387 Pages) RENESAS

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2-17

APPLICATION

2.2 Interrupt

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

(3)

Interrupt disable flag

The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable

flag controls the acceptance of interrupt request except BRK instruction.

When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the

acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set

to “0” with the CLI instruction.

When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”,

so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI

instruction within the interrupt processing routine. Figure 2.2.13 shows an example of multiple interrupts.

Table 2.2.2 List of interrupt bits according to interrupt source

INT0/Timer Z

INT1

Serial I/O1 reception

Serial I/O1 transmission/SCL, SDA

Timer X

Timer Y

Timer 1

Timer 2

CNTR0/SCL, SDA

CNTR1/Serial I/O3 reception

Serial I/O2/Timer Z

INT2/I2C

INT3

INT4/CNTR2

A/D converter/Serial I/O3 transmission

Interrupt enable bit

Address

003E16

003F16

Bit

Interrupt request bit

Address

003C16

003D16

Bit

Interrupt source

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