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M38041FEHKP 数据表(PDF) 175 Page - Renesas Technology Corp

部件名 M38041FEHKP
功能描述  8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  387 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M38041FEHKP 数据表(HTML) 175 Page - Renesas Technology Corp

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2-51
APPLICATION
2.4 Serial interface
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3804 Group (Spec.H)
Fig. 2.4.6 Structure of UART1 control register
Fig. 2.4.7 Structure of UART3 control register
UART1 control register
b7 b6 b5 b4 b3 b2 b1 b0
UART1 control register
(UART1CON: address 001B16)
b
0
0
0: 8 bits
1: 7 bits
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Stop bit length
selection bit (STPS)
P45/TxD1 P-channel
output disable bit
(POFF)
Parity selection bit
(PARS)
Functions
Name
At reset R W
1
0
0
0
2
3
4
5
6
1
7
1
✕
✕
✕
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “1”.
0
1
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
0: CMOS output
(in output mode)
1: N-channel open-drain
output (in output mode)
UART3 control register
b7 b6 b5 b4 b3 b2 b1 b0
UART3 control register
(UART3CON: address 003316)
b
0
0
0: 8 bits
1: 7 bits
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Stop bit length
selection bit (STPS)
P35/TxD3 P-channel
output disable bit
(POFF)
Parity selection bit
(PARS)
Functions
Name
At reset R W
1
0
0
0
2
3
4
5
6
1
7
1
✕
✕
✕
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “1”.
0
1
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
0: CMOS output
(in output mode)
1: N-channel open-drain
output (in output mode)



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