M38044FEHKP datasheet(197/387 Pages) RENESAS

197 / 387 page

2-73

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Control procedure :

q Control in the master unit

After setting the relevant registers shown in Figure 2.4.35, the master unit starts transmission or

reception of 1-byte data by writing transmission data to the transmit buffer register.

To perform the communication in the timing shown in Figure 2.4.34, take the timing into account

and write transmission data. Additionally, read out the reception data when the serial I/O1 transmit

interrupt request bit is set to “1,” or before the next transmission data is written to the transmit

buffer register.

Figure 2.4.36 shows a control procedure of the master unit using timer interrupts.

Fig. 2.4.36 Control procedure of master unit

Interrupt processing routine

executed every 488

µs

Write a transmission data

Read a reception data

Within a block transfer

period?

Complete to transfer a

block?

RTI

Write the first transmission data

(first byte) in a block

Count a block interval counter

Start a block transfer?

Generate a certain block interval by

using a timer or other functions.

Check the block interval counter and

determine to start a block transfer.

CLT (Note 1)

CLD (Note 2)

Push register to stack

Note 1: When using the Index X mode flag (T).

Note 2: When using the Decimal mode flag (D).

Push the register used in the interrupt

processing routine into the stack.

Pop registers

Pop registers which is pushed to stack.

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