M38045FEHKP datasheet(173/387 Pages) RENESAS

173 / 387 page

2-49

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Fig. 2.4.4 Structure of Serial I/O1 control register

Serial I/O1 control register

b7 b6 b5 b4 b3 b2 b1 b0

Serial I/O1 control register

(SIO1CON: address 001A16)

Name

Functions

At reset R W

3 Transmit interrupt

source selection

bit (TIC)

Transmit enable bit

(TE)

0: Transmit disabled

1: Transmit enabled

0: I/O port (P47)

1: SRDY1 output pin

0: Receive disabled

1: Receive enabled

0: UART

1: Clock synchronous

serial I/O

Receive enable bit

(RE)

Serial I/O1 mode

selection bit (SIOM)

Serial I/O1 enable

bit (SIOE)

0: Transmit buffer empty

1: Transmit shift operation

completion

0: f(XIN)

1: f(XIN)/4

When clock synchronous

serial I/O is selected,

0: BRG output divided by 4

1: External clock input

When UART is selected,

0: BRG output divided by 16

1: External clock input

divided by16

0: Serial I/O1 disabled

(P44 to P47: normal I/O pins)

1: Serial I/O1 enabled

(P44 to P47: Serial I/O pins)

Serial I/O1

synchronous clock

selection bit (SCS)

BRG count source

selection bit (CSS)

SRDY1 output

enable bit (SRDY)

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