M38045FEHKP datasheet(183/387 Pages) RENESAS

183 / 387 page

2-59

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

2.4.5 Serial I/O1, serial I/O3 operation: stop and initialize

Serial I/O1 and serial I/O3 perform the same operation. In the following explanations when names of serial

I/O1 and serial I/O3 are different, serial I/O1s' are showed first and then serial I/O3s' in the marked ( ).

(1)

Clock synchronous serial I/O mode

sStop/initialize transmit operation when only transmitting

When using an internal clock, set the transmit enable bit and serial I/O1 enable bit (serial I/O3

enable bit) to “0”.

When using an external clock, set the transmit enable bit to “0”.

By setting the transmit enable bit to “0”, the transmit operations listed below will be stopped or

initialized. However, when using an internal clock, the clock is output in 8 pulses, even if the

transmit enable bit is set to “0” during transmit operations.

•Stop supply of shift clock to transmit shift register

•Initialize clock control circuit for transmit

•Transmit buffer empty flag = “0”

•Transmit shift register shift complete flag = “0”

•P45/TxD1 pin: input/output port P45 (P35/TxD3 pin: input/output port P35)

By setting the serial I/O1 enable bit (serial I/O3 enable bit) to “0”, pins P44/RxD1, P45/TxD1, P46/

SCLK1, and P47/SRDY1 (P34/RxD3, P35/TxD3, P36/SCLK3, P37/SRDY3 pins) all become I/O ports. As a

result, the internal clock cannot be output externally.

sStop/initialize receive operation when only receiving

When using an internal clock, set the receive enable bit and serial I/O1 enable bit (serial I/O3

enable bit) to “0”.

When using an external clock, set the receive enable bit or serial I/O1 enable bit (serial I/O3

enable bit) to “0”.

By setting the receive enable bit to “0”, the receive operations listed below will be stopped or

initialized. However, when using an internal clock, the clock is output in 8 pulses, even if the

receive enable bit is set to “0” during receive operations.

•Stop supply of shift clock to receive shift register

•Initialize clock control circuit for receive

•Error flags (over-run, parity, framing, and summing error flags) = “0”

•Receive buffer full flag = “0”

•P44/RxD1 pin: input/output port P44 (P34/RxD3 pin: input/output port P34)

By setting the serial I/O1 enable bit (serial I/O3 enable bit) to “0”, the receive operations listed

below will be stopped or initialized. As a result, the internal clock cannot be output externally.

•Stop supply of shift clock to receive shift register

•Initialize clock control circuit for receive

•Error flags (over-run, parity, framing, and summing error flags) = “0”

•Receive buffer full flag = “0”

•P44/RxD1, P45/TxD1, P46/SCLK1, P47/SRDY1 pins: I/O ports P44, P45, P46, P47

(P34/RxD3, P35/TxD3, P36/SCLK3, P37/SRDY3 pins: I/O ports P34, P35, P36, P37)

sStop/initialize receive/transmit operation when both receiving and transmitting

Set the transmit enable bit and receive enable bit to “0” simultaneously.

When using an internal clock, also set the serial I/O1 enable bit (serial I/O3 enable bit) to “0”.

(2)

UART Mode

sStop/initialize transmit operation

Set the transmit enable bit to “0”.

sStop/initialize receive operation

Set the receive enable bit to “0”.

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