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M38049FEHKP 数据表(PDF) 136 Page - Renesas Technology Corp |
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M38049FEHKP 数据表(HTML) 136 Page - Renesas Technology Corp |
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136 / 387 page  2-12 APPLICATION 2.2 Interrupt Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) 2.2.3 Interrupt source The 3804 group (Spec. H) ’s interrupts are a type of vector and occur by 16 sources among 23 sources: nine external, thirteen internal, and one software. These are vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to Tables 2.2.1. Table 2.2.1 Interrupt sources, vector addresses and priority Interrupt Request Generating Conditions Remarks Interrupt Source Low FFFC16 FFFA16 High FFFD16 FFFB16 Priority 1 2 Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Vector Addresses (Note 1) Reset (Note 2) INT0 Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At detection of either rising or falling edge of SCL or SDA At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of SCL or SDA At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow At detection of either rising or falling edge of INT2 input At completion of data transfer At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A/D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty At BRK instruction execution Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 3 4 5 6 7 8 9 10 External interrupt (active edge selectable) SCL, SDA Timer X Timer Y Timer 1 Timer 2 CNTR0 SCL, SDA CNTR1 Serial I/O3 reception Serial I/O2 Timer Z INT2 STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Non-maskable software interrupt 11 FFE916 FFE816 12 I2C INT3 INT4 CNTR2 A/D converter Serial I/O3 transmission BRK instruction 14 15 13 16 17 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 |
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