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PSMN1R7-30YL 数据表(PDF) 8 Page - NXP Semiconductors |
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PSMN1R7-30YL 数据表(HTML) 8 Page - NXP Semiconductors |
8 / 13 page PSMN1R7-30YL_1 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 01 — 11 September 2008 8 of 13 NXP Semiconductors PSMN1R7-30YL N-channel TrenchMOS logic level FET Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 14. Gate charge waveform definitions Fig 15. Gate-source voltage as a function of gate charge; typical values Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 03aa27 0 0.5 1 1.5 2 -60 0 60 120 180 Tj ( °C) a 003aaa508 VGS VGS(th) QGS1 QGS2 QGD VDS QG(tot) ID QGS VGS(pl) 003aac448 0 2 4 6 8 10 0 2040 6080 QG (nC) VGS (V) VDS = 19 (V) VDS = 12 (V) 003aac454 0 2000 4000 6000 10 -1 1 10 10 2 VDS (V) C (pF) Ciss Coss Crss |
类似零件编号 - PSMN1R7-30YL |
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类似说明 - PSMN1R7-30YL |
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