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AT89C5122DS-RDRUM 数据表(PDF) 121 Page - ATMEL Corporation |
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AT89C5122DS-RDRUM 数据表(HTML) 121 Page - ATMEL Corporation |
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121 / 208 page  121 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Reset Value = 0000 0000b Table 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h) 76543210 - EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST Bit Number Bit Mnemonic Description 7- Reserved The value read from these bits is always 0. Do not change this bit. 6EP6RST Endpoint 6 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. 5EP5RST Endpoint 5 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. 4EP4RST Endpoint 4 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. 3EP3RST Endpoint 3 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. 2EP2RST Endpoint 2 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. 1EP1RST Endpoint 1 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. 0EP0RST Endpoint 0 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. |
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