STM32F103xC datasheet(119/123 Pages) STMICROELECTRONICS

119 / 123 page

STM32F103xC, STM32F103xD, STM32F103xE

Revision history

Doc ID 14611 Rev 7

119/123

21-Jul-2008

Document status promoted from Preliminary Data to full datasheet.

FSMC (flexible static memory controller) on page 15 modified.

Number of complementary channels corrected in Figure 1:

STM32F103xC, STM32F103xD and STM32F103xE performance line

block diagram.

Power supply supervisor on page 17 modified and VDDA added to

Table 10: General operating conditions on page 42.

Table notes revised in Section 5: Electrical characteristics.

Capacitance modified in Figure 12: Power supply scheme on page 40.

Table 51: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) updated.

Table 52: SPI characteristics modified, th(NSS) modified in Figure 45:

SPI timing diagram - slave mode and CPHA = 0 on page 91.

Minimum SDA and SCL fall time value for Fast mode removed from

Table 50: I2C characteristics on page 88, note 1 modified.

IDD_VBAT values and some IDD values with regulator in run mode added

to Table 17: Typical and maximum current consumptions in Stop and

Standby modes on page 48.

Table 30: Flash memory endurance and data retention on page 61

updated.

tsu(NSS) modified in Table 52: SPI characteristics on page 90.

EO corrected in Table 61: ADC accuracy on page 100. Figure 54:

Typical connection diagram using the ADC on page 101 and note below

corrected.

Typical TS_temp value removed from Table 63: TS characteristics on

page 105.

Section 6.1: Package mechanical data on page 106 updated.

Small text changes.

Table 72.

Document revision history

Date

Revision

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STM32F103xC 数据表(PDF) 119 Page - STMicroelectronics

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