MPC8377ECVRALGA datasheet(107/124 Pages) FREESCALE

107 / 124 page

MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

107

Clocking

As described in Section 23, “Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 76

and Table 77 show the expected frequency values for the CSB frequency for select csb_clk to

CLKIN/PCI_SYNC_IN ratios.

The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 75.

Table 74. System PLL Multiplication Factors

RCWL[SPMF]

System PLL Multiplication Factor

0000

Reserved

0001

Reserved

0010

× 2

0011

× 3

0100

× 4

0101

× 5

0110

× 6

0111–1111

× 7 to × 15

Table 75. System PLL VCO Divider

RCWL[SVCOD]

VCO Division Factor

Table 76. CSB Frequency Options for Host Mode

CFG_CLKIN_DIV

at Reset 1

SPMF

csb_clk :

Input Clock

Ratio 2

Input Clock Frequency (MHz) 2

33.33

66.67

csb_clk

Frequency (MHz)

—

High

0010

2 : 1

133

High

0011

3 : 1

100

—

High

0100

4 : 1

100

133

—

High

0101

5 : 1

125

167

—

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