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数据搜索系统，热门电子元器件搜索 |
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ATtiny48 数据表(PDF) 120 Page - ATMEL Corporation |
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ATtiny48 数据表(HTML) 120 Page - ATMEL Corporation |
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120 / 266 page  120 8008C–AVR–03/09 ATtiny48/88 Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi- bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 14.4 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 14-3 and Figure 14-4. Figure 14-3. SPI Transfer Format with CPHA = 0 Figure 14-4. SPI Transfer Format with CPHA = 1 Bit 1 Bit 6 LSB MSB SCK (CPOL = 0) mode 0 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SCK (CPOL = 1) mode 2 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 MSB first (DORD = 0) LSB first (DORD = 1) SCK (CPOL = 0) mode 1 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SCK (CPOL = 1) mode 3 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB MSB first (DORD = 0) LSB first (DORD = 1) |
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