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ATtiny88 数据表(PDF) 103 Page - ATMEL Corporation |
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ATtiny88 数据表(HTML) 103 Page - ATMEL Corporation |
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103 / 266 page  103 8008C–AVR–03/09 ATtiny48/88 Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 12-11 shows the same timing data, but with the prescaler enabled. Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk_I/O/8) Figure 12-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. clk Tn (clk I/O/1) OCFnx clk I/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clk I/O clk Tn (clk I/O/8) |
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