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ATtiny88 数据表(PDF) 114 Page - ATMEL Corporation |
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ATtiny88 数据表(HTML) 114 Page - ATMEL Corporation |
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114 / 266 page ![]() 114 8008C–AVR–03/09 ATtiny48/88 When the TSM bit is written to zero, the PSRSYNC bit are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bits 6..1 – Reserved These bits are reserved and will always read zero. • Bit 0 – PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. |
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