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数据搜索系统，热门电子元器件搜索 |
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ATmega328P 数据表(PDF) 133 Page - ATMEL Corporation |
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ATmega328P 数据表(HTML) 133 Page - ATMEL Corporation |
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133 / 448 page  133 8161D–AVR–10/09 ATmega48PA/88PA/168PA/328P Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk_I/O/8) Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 15-12. Timer/Counter Timing Diagram, no Prescaling OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clk I/O clk Tn (clk I/O/8) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk Tn (clk I/O/1) clk I/O |
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