SC16C2552B_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 12 February 2009

5 of 38

NXP Semiconductors

SC16C2552B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

RTSA

36

O

Request to Send A, B (active LOW). These outputs are associated with individual UART

channels A through B. A logic 0 on the RTSn pin indicates the transmitter is ready to

transmit data. Writing a logic 1 in the modem control register MCR[1] will set this pin to a

logic 0, indicating that the transmitter is ready to transmit data. After a reset, this pin will be

set to a logic 1.

RTSB

23

O

RXA

39

I

Receive data A, B. These inputs are associated with individual serial channel data to the

SC16C2552B receive input circuits A through B. The RXn signal will be a logic 1 during

reset, idle (no data). During the local Loopback mode, the RXn input pin is disabled and TXn

data is connected to the UART RXn input, internally.

RXB

25

I

TXA

38

O

Transmit data A, B. These outputs are associated with individual serial transmit channel

data from the SC16C2552B. The TXn signal will be a logic 1 during reset, idle (no data), or

when the transmitter is disabled. During the local Loopback mode, the TXn output pin is

disabled and TXn data is internally connected to the UART RXn input.

TXB

26

O

TXRDYA1

O

Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR status for

individual transmit channels (A, B). TXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA,

TXRDYB buffer ready status is indicated by logic 0, i.e., at least one location is empty and

available in the FIFO or THR. This signal can also be used for single mode transfers (DMA

mode 0).

TXRDYB

32

O

33, 44

I

Power supply input.

XTAL1

11

I

Crystal or external clock input. Functions as a crystal input or as an external clock input.

A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit.

Alternatively, an external clock can be connected to this pin to provide custom data rates.

See Section 6.5 “Programmable baud rate generator”.

XTAL2

13

O

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator

output or buffered clock output. Should be left open if an external clock is connected to

XTAL1.

Table 2.

Symbol

Pin

Type

Description