SC16C2552B datasheet(6/38 Pages) NXP

部件名	SC16C2552B

功能描述	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

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制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

6 of 38

NXP Semiconductors

SC16C2552B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.

Functional description

The SC16C2552B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character. Data integrity is ensured by attaching a parity bit to the data character. The

parity bit is checked by the receiver for any transmission bit errors. The SC16C2552B is

fabricated with an advanced CMOS process.

The SC16C2552B is an upward solution that provides a dual UART capability with

16 bytes of transmit and receive FIFO memory, instead of none in the 16C450. The

SC16C2552B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C2552B by the transmit and receive FIFOs. This allows the external processor to

handle more networking tasks within a given time. In addition, the four selectable receive

FIFO trigger interrupt levels are uniquely provided for maximum data throughput

performance, especially when operating in a multi-channel environment. The FIFO

memory greatly reduces the bandwidth requirement of the external controlling CPU,

increases performance, and reduces power consumption.

The SC16C2552B is capable of operation up to 1.5 Mbit/s with a 24 MHz crystal. With a

crystal or external clock input of 7.3728 MHz, the user can select data rates up to

460.8 kbit/s.

The rich feature set of the SC16C2552B is available through internal registers. Selectable

receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface

controls are all standard features.

6.1 UART A-B functions

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC16C2552B package, and an external serial device. A

logic 0 on chip select pin CS and a logic 1 on CHSEL allows the user to conﬁgure, send

data, and/or receive data via UART channel A. A logic 0 on chip select pin CS and a

logic 0 on CHSEL allows the user to conﬁgure, send data, and/or receive data via UART

channel B. Individual channel select functions are shown in Table 3.

During a write mode cycle, the setting of AFR[0] to a logic 1 will override the CHSEL

selection and allow a simultaneous write to both UART channel sections. This functional

capability allows the registers in both UART channels to be modiﬁed concurrently, saving

individual channel initialization time. Caution should be considered, however, when using

this capability. Any in-process serial data transfer may be disrupted by changing an active

channel’s mode.

Table 3.

Serial port selection

Chip select

UART select

CS = 1

none

CS = 0

UART channel selected as follows:

CHSEL = 1: UART channel A

CHSEL = 0: UART channel B

类似零件编号 - SC16C2552B

制造商	部件名	数据表	功能描述
NXP Semiconductors	SC16C2552	579Kb / 38P	Dual UART with 16-byte transmit and receive FIFOs Rev. 03-20 June 2003
NXP Semiconductors	SC16C2552IA44	579Kb / 38P	Dual UART with 16-byte transmit and receive FIFOs Rev. 03-20 June 2003

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制造商	部件名	数据表	功能描述
NXP Semiconductors	SC16C2550B	211Kb / 43P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 04-15 February 2007
	SC16C2550B	221Kb / 43P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 05-12 January 2009
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	SC16C752B	226Kb / 47P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Rev. 05-2 October 2008
	SC16C754B	259Kb / 50P	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 02-13 June 2005
	SC16C754B	252Kb / 51P	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 04-6 October 2008

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SC16C2552B 数据表(PDF) 6 Page - NXP Semiconductors

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类似零件编号 - SC16C2552B

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SC16C2552B 数据表(PDF) 6 Page - NXP Semiconductors

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类似说明 - SC16C2552B

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