PPC8572ECVTARLD datasheet(102/140 Pages) FREESCALE

102 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

102

Freescale Semiconductor

Package Description

18.3

Pinout Listings

Table 75 provides the preliminary pin-out listing for the MPC8572E 1023 FC-PBGA package. This table

is included for preliminary information purposes only.

Table 75. MPC8572E Pinout Listing

Signal

Signal Name

Package Pin Number

Pin Type

Power

Supply

Notes

DDR SDRAM Memory Interface 1

D1_MDQ[0:63]

Data

D15, A14, B12, D12,

A15, B15, B13, C13,

C11, D11, D9, A8, A12,

A11, A9, B9, F11, G12,

K11, K12, E10, E9,

J11, J10, G8, H10, L10,

M11, F10, G9, K9, K8,

AC6, AC7, AG8, AH9,

AB6, AB8, AE9, AF9,

AL8, AM8, AM10,

AK11, AH8, AK8, AJ10,

AK10, AL12, AJ12,

AL14, AK14, AL11,

AM11, AK13, AM14,

AM15, AJ16, AL18,

AM18, AJ15, AL15,

AK17, AM17

I/O

GVDD

—

D1_MECC[0:7]

Error Correcting Code

M10, M7, R8, T11, L12,

L11, P9, R10

I/O

GVDD

—

D1_MAPAR_ERR

Address Parity Error

GVDD

—

D1_MAPAR_OUT

Address Parity Out

GVDD

—

D1_MDM[0:8]

Data Mask

C14, A10, G11, H9,

AD7, AJ9, AM12,

AK16, N11

OGVDD

—

D1_MDQS[0:8]

Data Strobe

A13, C10, H12, J7,

AE8, AM9, AM13,

AL17, N9

I/O

GVDD

—

D1_MDQS[0:8]

Data Strobe

D14, B10, H13, J8,

AD8, AL9, AJ13,

AM16, P10

I/O

GVDD

—

D1_MA[0:15]

Address

Y7, W8, U6, W9, U7,

V8, Y11, V10, T6, V11,

AA10, U9, U10, AD11,

T8, P7

OGVDD

—

D1_MBA[0:2]

Bank Select

AA7, AA8, R7

GVDD

—

D1_MWE

Write Enable

AC12

GVDD

—

D1_MCAS

Column Address Strobe

AC9

GVDD

—

D1_MRAS

Row Address Strobe

AB12

GVDD

—

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