STM32F415OG datasheet(126/186 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F415xx, STM32F417xx

126/186

DocID022063 Rev 4

USB HS characteristics

Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from

tests performed under the ambient temperature, fHCLK frequency summarized in Table 61

and VDD supply voltage conditions summarized in Table 60, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD.

Refer to Section Section 5.3.16: I/O port characteristics for more details on the

input/outputcharacteristics.

Table 59. USB OTG FS electrical characteristics(1)

1. Guaranteed by design, not tested in production.

Driver characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Rise time(2)

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

CL = 50 pF

420

Fall time(2)

CL = 50 pF

trfm

Rise/ fall time matching

tr/tf

110

VCRS

Output signal crossover voltage

1.3

2.0

Table 60. USB HS DC electrical characteristics

Symbol

Parameter

Min.(1)

1. All the voltages are measured from the local ground potential.

Max.(1)

Unit

Input level

VDD

USB OTG HS operating voltage

2.7

3.6

Table 61. USB HS clock timing parameters(1)

Parameter

Symbol

Min

Nominal

Max

Unit

fHCLK value to guarantee proper operation of

USB HS interface

MHz

Frequency (first transition)

8-bit ±10%

FSTART_8BIT

MHz

Frequency (steady state) ±500 ppm

FSTEADY

59.97

60.03

MHz

Duty cycle (first transition)

8-bit ±10%

DSTART_8BIT

Duty cycle (steady state) ±500 ppm

DSTEADY

49.975

50.025

Time to reach the steady state frequency and

duty cycle after the first transition

TSTEADY

1.4

Clock startup time after the

de-assertion of SuspendM

Peripheral

TSTART_DEV

5.6

Host

TSTART_HOST

PHY preparation time after the first transition

of the input clock

TPREP

µs

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