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STM32F407IGH6 数据表(PDF) 147 Page - STMicroelectronics |
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STM32F407IGH6 数据表(HTML) 147 Page - STMicroelectronics |
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147 / 185 page  DocID022152 Rev 4 147/185 STM32F405xx, STM32F407xx Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Table 82. Synchronous non-multiplexed PSRAM write timings(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK -ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 7 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 6 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 2 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns |
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