STM32F103RCT7 datasheet(128/130 Pages) STMICROELECTRONICS

128 / 130 page

Revision history

STM32F103xC, STM32F103xD, STM32F103xE

128/130

Doc ID 14611 Rev 8

21-Jul-2009

Figure 1: STM32F103xC, STM32F103xD and STM32F103xE

performance line block diagram updated.

Note 5 updated and Note 4 added in Table 5: High-density

STM32F103xx pin definitions.

VRERINT and TCoeff added to Table 13: Embedded internal reference

voltage.

Table 16: Maximum current consumption in Sleep mode, code running

from Flash or RAM modified.

fHSE_ext min modified in Table 21: High-speed external user clock

characteristics.

CL1 and CL2 replaced by C in Table 23: HSE 4-16 MHz oscillator

characteristics and Table 24: LSE oscillator characteristics (fLSE =

32.768 kHz), notes modified and moved below the tables.

Note 1 modified below Figure 22: Typical application with an 8 MHz

crystal. Table 25: HSI oscillator characteristics modified. Conditions

removed from Table 27: Low-power mode wakeup timings.

Jitter added to Table 28: PLL characteristics.

Figure 47: Recommended NRST pin protection modified.

In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read

timings: th(BL_NOE) and th(A_NOE) modified.

In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write

timings: th(A_NWE) and th(Data_NWE) modified.

In Table 33: Asynchronous multiplexed PSRAM/NOR read timings:

th(AD_NADV) and th(A_NOE) modified.

In Table 34: Asynchronous multiplexed PSRAM/NOR write timings:

th(A_NWE) modified.

In Table 35: Synchronous multiplexed NOR/PSRAM read timings:

th(CLKH-NWAITV) modified.

In Table 40: Switching characteristics for NAND Flash read and write

cycles: th(NOE-D) modified.

Table 53: SPI characteristics modified. Values added to Table 54: I2S

characteristics and Table 55: SD / MMC characteristics.

CADC and RAIN parameters modified in Table 59: ADC characteristics.

RAIN max values modified in Table 60: RAIN max for fADC = 14 MHz.

Table 63: DAC characteristics modified. Figure 61: 12-bit buffered /non-

buffered DAC added.

Figure 64: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array

package outline and Table 67: LFBGA100 - 10 x 10 mm low profile fine

pitch ball grid array package mechanical data updated.

24-Sep-2009

Number of DACs corrected in Table 3: STM32F103xx family.

IDD_VBAT updated in Table 17: Typical and maximum current

consumptions in Stop and Standby modes.

Figure 16: Typical current consumption on VBAT with RTC on vs.

temperature at different VBAT values added.

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to

IEC 61967-2 in Section 5.3.11: EMC characteristics on page 83.

Table 63: DAC characteristics modified. Small text changes.

Table 75.

Document revision history

Date

Revision

Changes

STM32F103RCT7 数据表(PDF) 128 Page - STMicroelectronics

STM32F103RCT7 数据表(HTML) 128 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载