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STM32L151VD 数据表(PDF) 118 Page - STMicroelectronics |
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STM32L151VD 数据表(HTML) 118 Page - STMicroelectronics |
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118 / 140 page  Electrical characteristics STM32L151xD STM32L152xD 118/140 Doc ID 022027 Rev 6 dOffset/dT(1) Offset error temperature coefficient (code 0x800) VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 °C DAC output buffer OFF -20 -10 0 µV/°C VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 °C DAC output buffer ON 020 50 Gain(1) Gain error(7) CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer ON - +0.1 / -0.2% +0.2 / -0.5% % No RLOAD, CL ≤ 50 pF DAC output buffer OFF - +0 / -0.2% +0 / -0.4% dGain/dT(1) Gain error temperature coefficient VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 °C DAC output buffer OFF -10 -2 0 µV/°C VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 °C DAC output buffer ON -40 -8 0 TUE(1) Total unadjusted error CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer ON -12 30 LSB No RLOAD, CL ≤ 50 pF DAC output buffer OFF -8 12 tSETTLING Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes till DAC_OUT reaches final value ±1LSB CL ≤ 50 pF, RL ≥ 5 kΩ - 7 12 µs Update rate Max frequency for a correct DAC_OUT change (95% of final value) with 1 LSB variation in the input code CL ≤ 50 pF, RL ≥ 5 kΩ -1 Msps tWAKEUP Wakeup time from off state (setting the ENx bit in the DAC Control register)(8) CL ≤ 50 pF, RL ≥ 5 kΩ - 9 15 µs PSRR+ VDDA supply rejection ratio (static DC measurement) CL ≤ 50 pF, RL ≥ 5 kΩ - -60 -35 dB 1. Data based on characterization results. 2. Connected between DAC_OUT and VSSA. 3. Difference between two consecutive codes - 1 LSB. 4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2. Table 67. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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